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74FST3384 10-Bit Low Power Bus Switch
The ON Semiconductor 74FST3384 is a 10-bit low power bus switch. The device is CMOS TTL compatible when operating between 4 and 5.5 Volts. The device exhibits extremely low RON and adds nearly zero propagation delay. The device adds no noise or ground bounce to the system. * RON t 4 W Typical * Less Than 0.25 ns-Max Delay Through Switch * Nearly Zero Standby Current * No Circuit Bounce * Control Inputs are TTL/CMOS Compatible * Pin-For-Pin Compatible With QS3384, FST3384, CBT3384 * All Popular Packages: SOIC-24, TSSOP-24, QSOP-24
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MARKING DIAGRAMS
24 24 1 SO-24 DW SUFFIX CASE 751E 1 FST3384 AWLYWW
OE1 B0 A0 A1 B1 B2 A2 A3 B3 B4 A4 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC B9 A9 A8 B8 B7 A7 A6 B6 B5 A5 OE2
24 24 1 TSSOP-24 DT SUFFIX CASE 948H 1 FST 3384 ALYW
24 24 1 QSOP-24 QS SUFFIX CASE 492B Function Connect Connect Connect Disconnect A L, WL Y, YY W, WW = = = = FST3384 AWLYYWW 1
Figure 1. 24-Lead Pinout
TRUTH TABLE
OE1 L L H H OE2 L H L H B0-B4 A0-A4 A0-A4 HIGH-Z State HIGH-Z State B5-B9 A5-A9 HIGH-Z State A5-A9 HIGH-Z State
Assembly Location Wafer Lot Year Work Week
ORDERING INFORMATION
Device 74FST3384DW 74FST3384DWR2 74FST3384DT 74FST3384DTR2 Package SO-24 SO-24 TSSOP-24 TSSOP-24 QSOP-24 QSOP-24 Shipping 48 Units/Rail 2500 Units/Reel 96 Units/Rail 2500 Units/Reel 96 Units/Rail 2500 Units/Reel
NOTE: H = HIGH Voltage Level, L = LOW Voltage Level
PIN NAMES
Pin OE1, OE2 A0-A9 B0-B9 Description Bus Switch Enable Bus A Bus B
74FST3384QS 74FST3384QSR
(c) Semiconductor Components Industries, LLC, 2002
1
May, 2002 - Rev. 4
Publication Order Number: 74FST3384/D
74FST3384
A0 B0
A4
B4
A5
B5
A9
B9
OE1
OE2
Figure 2. Logic Diagram
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74FST3384
MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG TL TJ qJA DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance SOIC TSSOP QSOP VI t GND VO t GND Parameter Value *0.5 to )7.0 *0.5 to )7.0 *0.5 to )7.0 *50 *50 128 $100 $100 *65 to )150 260 )150 125 170 200 Level 1 Oxygen Index: 28 to 34 Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Above VCC and Below GND at 85C (Note 4) UL 94 V-0 @ 0.125 in u2000 u200 N/A $500 V Unit V V V mA mA mA mA mA C C C C/W
MSL FR VESD
Moisture Sensitivity Flammability Rating ESD Withstand Voltage
ILATCH-UP
Latch-Up Performance
mA
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum-rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. 1. Tested to EIA/JESD22-A114-A. 2. Tested to EIA/JESD22-A115-A. 3. Tested to JESD22-C101-A. 4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO TA Dt/DV Supply Voltage Input Voltage Output Voltage Operating Free-Air Temperature Input Transition Rise or Fall Rate Switch I/O Switch Control Input VCC = 5.0 V $ 0.5 V Parameter Operating, Data Retention Only (Note 5) (HIGH or LOW State) Min 4.0 0 0 *40 0 Max 5.5 5.5 5.5 )85 DC 5 Unit V V V C ns/V
5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.
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74FST3384
DC ELECTRICAL CHARACTERISTICS
VCC (V) 4.5 4.0 to 5.5 4.0 to 5.5 0 v VIN v 5.5 V 0 v A, B v VCC VIN = 0 V, IIN = 64 mA VIN = 0 V, IIN = 30 mA VIN = 2.4 V, IIN = 15 mA VIN = 2.4 V, IIN = 15 mA ICC DICC Quiescent Supply Current Increase In ICC per Input VIN = VCC or GND, IOUT = 0 One input at 3.4 V, Other inputs at VCC or GND 5.5 5.5 4.5 4.5 4.5 4.0 5.5 5.5 4 4 8 11 2.0 0.8 $1.0 $1.0 7 7 15 20 3 2.5 mA mA TA = *405C to )855C Min Typ* Max *1.2 Unit V V V mA mA W
Symbol VIK VIH VIL II IOZ RON
Parameter Clamp Diode Resistance High-Level Input Voltage Low-Level Input Voltage Input Leakage Current OFF-STATE Leakage Current Switch On Resistance (Note 6) IIN = *18mA
Conditions
*Typical values are at VCC = 5.0 V and TA = 25C. 6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the two (A or B) pins.
AC ELECTRICAL CHARACTERISTICS
TA = *405C to )855C CL = 50 pF, RU = RD = 500 W VCC = 4.5-5.5 V Symbol tPHL, tPLH tPZH, tPZL tPHZ, tPLZ Parameter Prop Delay Bus to Bus (Note 7) Output Enable Time, IOE to Bus A, B Output Disable Time, IOE to Bus A, B Conditions VI = OPEN VI = OPEN for tPZH VI = OPEN for tPHZ 1.0 1.0 Min Max 0.25 5.7 5.2 VCC = 4.0 V Min Max 0.25 6.2 5.5 Unit ns ns ns
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE (Note 8)
Symbol CIN CI/O Parameter Control Pin Input Capacitance Port Input/Output Capacitance VCC = 5.0 V VCC, OE = 5.0 V Conditions Typ 6 13 Max Unit pF pF
8. TA = )25C, f = 1 MHz, Capacitance is characterized but not tested.
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74FST3384
AC Loading and Waveforms
VI FROM OUTPUT UNDER TEST CL * 500 W
500 W
NOTES: 1. Input driven by 50 W source terminated in 50 W. 2. CL includes load and stray capacitance. *CL = 50 pF
Figure 3. AC Test Circuit
tf = 2.5 nS 90 % SWITCH INPUT 1.5 V 10 % tPLH 90 % 1.5 V
tf = 2.5 nS 3.0 V
10 % tPLH
GND VOH
1.5 V OUTPUT
1.5 V VOL
Figure 4. Propagation Delays
tf = 2.5 nS tf = 2.5 nS ENABLE INPUT 90 % 1.5 V 10 % tPZL OUTPUT 10 % 90 % 1.5 V GND tPZL 3.0 V
1.5 V
VOL + 0.3 V VOL tPHZL VOH
tPZH
1.5 V OUTPUT
VOH - 0.3 V
Figure 5. Enable/Disable Delays
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74FST3384
PACKAGE DIMENSIONS
-A-
24 13
SO-24 D SUFFIX CASE 751E-04 ISSUE E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45 _
M
22X
G
K
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74FST3384
PACKAGE DIMENSIONS
TSSOP-24 DT SUFFIX CASE 948H-01 ISSUE A
24X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 7.70 7.90 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.303 0.311 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
2X
L/2
24
13
L
PIN 1 IDENT. 1 12
B -U-
0.15 (0.006) T U
S
A -V-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
N K K1 J1
0.25 (0.010) M -W-
SECTION N-N J
CCC EE CCC EE
N F DETAIL E DETAIL E
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74FST3384
PACKAGE DIMENSIONS
QSOP-24 QS SUFFIX CASE 492B-01 ISSUE O
-A- R U -B-
Q H x 45_
MOLD PIN MARK
RAD. 0.013 X 0.005 DP. MAX RAD. 0.005-0.010 TYP
L
P 0.25 (0.010)
M
G T
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE ONLY). BOTTOM PACKAGE DIMENSION SHALL FOLLOW THE DIMENSION STATED IN THIS DRAWING. 4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 6 MILS PER SIDE. 5. BOTTOM EJECTOR PIN WILL INCLUDE THE COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D. INCHES DIM MAX MIN A 0.337 0.344 B 0.150 0.157 C 0.061 0.068 D 0.008 0.012 F 0.016 0.035 G 0.025 BSC H 0.008 0.018 J 0.0098 0.0075 K 0.004 0.010 L 0.230 0.244 M 0_ 8_ N 0_ 7_ P 0.027 0.037 Q 0.035 DIA R 0.035 0.045 U 0.035 0.045 V 0_ 8_ MILLIMETERS MAX MIN 8.56 8.74 3.81 3.99 1.55 1.73 0.20 0.31 0.41 0.89 0.64 BSC 0.20 0.46 0.249 0.191 0.10 0.25 5.84 6.20 0_ 8_ 0_ 7_ 0.69 0.94 0.89 DIA 0.89 1.14 0.89 1.14 0_ 8_
DETAIL E
V N 8 PL K -T- C
24 PL
J M
D
M
SEATING PLANE
F DETAIL E
0.25 (0.010)
TB
S
A
S
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
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74FST3384/D

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